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Full Duplex in Action at CableLabs 2017 Summer Conference

- August 7, 2017 - 3 Comments

By John Chapman, Cisco Fellow, CTO, Cable Access, Cisco

For the first time in the United States, we’ll be hosting our Full Duplex (FDX) DOCSIS proof of concept with Intel at the CableLabs Summer Conference this week. We unveiled the demo this past May at ANGA.COM

FDX: Groundbreaking Technology So why is FDX so important?

An all-DOCSIS 3.1 downstream plant would allow operators to reach speeds of 10 Gigabits per second in the downstream. With FDX DOCSIS, the upstream would be extended to 5 Gbps. And if a node contains one forward path and two reverse paths, then that optical node would have 10 Gbps capacity in both the downstream and upstream, matching the 10 Gbps wavelength used to feed the digital optical node. So with DOCSIS FDX, you’d have the equivalent to a fiber wavelength – without actually running fiber.

About the FDX Demonstration

The proof of concept demonstration is only 96 MHz symmetrical, because we are relying on current technology, and today’s cable modems “top out” at an upstream spectral location of 204 MHz. The 96 MHz shared spectrum in the demo will have a downstream rate of 890 Mbps (with 4K QAM) and an upstream rate of 680 Mbps (with 1K QAM).

Here’s what you’ll see at the CableLabs conference:

A 96 MHz chunk of spectrum, located between 108 MHz and 204 MHz, with traffic moving simultaneously up and downstream. We’ll show a node transmitting and receiving at the same time, on the same spectrum.

Watch the Cisco and Intel ANGA.COM demo on periscope.

As you can see, the capabilities presented in our FDX demo have expanded significantly. At last year’s CableLab’s conference, we gave you a taste of what we were working on with FDX and demonstrated the echo canceller functionality – no packets, just raw bits. This year’s demo is the real deal.

Intel’s contribution to the demonstration is its FPGA (Field Programmable Gate Array) silicon, used in the remote PHY device (RPD) and the Intel® Puma™ 7 SoC, used in the cable modem devices. The Intel FPGA is valuable for its role in rapidly responding to marketplace developments – like FDX. It was a fully programmable, DOCSIS 3.1 Remote PHY system on chip (SoC) platform running OpenRPD open source software. The Intel Puma™ 7 SoC provides robustness against interference that enables the downstream traffic to be received from the CMTS while the other modem is sending upstream data in the same spectrum.

The magic in the FPGA silicon is our (substantial) FDX work on echo cancellation. One way to envision this is to think about the noise-canceling headphones people tend to wear on airplanes. The headphones listen to the ambient noise of the plane, and create an inverse signal that cancels it out. In the case of FDX DOCSIS, what one modem transmits, the other sees as noise. An FDX echo canceller, like we’re demonstrating at CableLabs Summer Conference, removes multiples of such “echos.”

Why is this happening? Ultimately, echo cancellation is an example of what can be achieved — when you have a whole lot of gates, and a whole lot of DSP horsepower.

What FDX Means to the Cable Industry

We believe FDX ultimately means that DOCSIS will live on as industry standard, because FDX creates what is essentially a fiber equivalent, throughput-wise, with coax. Moving 10 Gbps downstream, toward nodes, is already within reach; two upstream node ports running FDX yields 10 Gigs upstream.

See you in Keystone, CO – August 6-9

Make sure you stop by and see us @CableLabs Summer Conference in Keystone #Colorado on August 6. Have questions and comments, Tweet us @CiscoSP360.

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3 Comments

  1. Excellent progress. Looking forward to major improvements in service performance and capabilities.

  2. Looking great!

    Great post.

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