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Today’s guest blog entry comes from Daniel Holmes, an Applications Developers at the EPCC

I met Jeff at EuroMPI in September, and he has invited me to write a few words on my experience of developing an MPI library.

My PhD involved building a message passing library using C#; not accessing an existing MPI library from C# code but creating a brand new MPI library written entirely in pure C#. The result is McMPI (Managed-code MPI), which is compliant with MPI-1 – as far as it can be given that there are no language bindings for C# in the MPI Standard. It also has reasonably good performance in micro-benchmarks for latency and bandwidth both in shared-memory and distributed-memory.

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EuroMPI 2013: CFP

It’s that time of year again — time to start preparing for Euro MPI 2013!

Next year, we’ll be heading to Madrid, Spain September 15-18.   Here’s a snipit from the call for papers:

Topics of interest include, but are not limited to:

  • MPI implementation issues and improvements
  • Extensions to and shortcomings of MPI
  • Tools and environments for MPI
  • Hybrid and heterogeneous programming with MPI and other interfaces

Come join us for some sangria in scenic Madrid next year.  Submission deadline is March 29th.

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Cisco ultra low latency support for MPI

My team demonstrated our new ultra-low latency Ethernet solution in the Cisco booth at SC this past week (it was so busy that I didn’t get to post this until it was all over!).

The short version is that we have implemented operating system bypass and NIC hardware offload via the Linux OpenFabrics verbs API stack. We call it “userspace NIC”, or “USNIC”.

But let’s cut to the chase — what’s the performance?  Let’s break it down:

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MPICH 3.0 RC released

The MPICH folks have released an RC candidate for MPICH 3.0:

A new preview release of MPICH, 3.0rc1, is now available for download. The primary focus of this release is to provide full support for the MPI-3 standard.  Other smaller features including support for ARM v7 native atomics are also included.

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Algo Boost Series: Part 3 Commitment to Innovation with Nexus 3548

On November 5th I posted part 2 of the Algo Boost series with a fantastic discussion around Customer proof points on the Nexus 3548.  In our third and final segment in the series I interviewed Chih-Tsung Huang, Director of Engineering in the Server, Switching, & Virtualization Product Group to shed some light on Cisco’s continued commitment to innovate with Algo Boost technology.

GD: What is the primary difference between existing Nexus 3000 switches and the new Nexus 3548?  And how do we differentiate from the competition?

CH: As we all know, the current generation Nexus 3000 uses merchant silicon while the new Nexus 3548 uses a full layer 2 bridging and layer 3 routing Cisco ASIC – designed and built from ground up to optimize switch latency. Prior to the Nexus 3548 announcement, industry best was greater than 500 nanoseconds.

One of the stated elements of our corporate culture is “No Technology Religion”.  The underlying concept is that we have the freedom to choose the solution that allows us to best meet our customer’s needs and not get locked into ideological silos.

Cisco continues to invest and drive innovations and standardization efforts with the development of our own ASICs because this allows us to deliver a complete value add solution to our customers.  However, we do take advantage of merchant silicon in specific use cases where features and innovation are not needed.

GD: Does the introduction of Algo Boost indicate a complete shift away from merchant silicon?

CH: Absolutely not.  Cisco has and will continue to adopt a flexible silicon strategy, meaning we will buy off-the-shelf ASICs when they can immediately fill a market need, and we continue to add value through silicon innovation by designing our own ASICs. The Nexus 3548 is an example of a highly integrated Software, Hardware and ASIC solution that cannot be achieved with off the shelf components.

GD: It sounds like we are very much committed to developing our own ASICs. How many ASICS are used in Cisco Solutions today, and how much do we invest in R&D?

CH: Cisco has developed hundreds of ASICs to perform various forwarding functions in switches and routers.  Cisco has developed over 20 ASICs to power the Nexus portfolio alone. We have an annual R&D budget of $5.8 billion which is greater than Juniper’s entire revenues and roughly equal to the R&D budgets of HP and Huawei combined.

GD: Algo Boost clearly addresses needs in the financial sector. Are there any other segments that will benefit from these groundbreaking features?

CH: Since mid-2011, the Nexus 3000 family has had a significant presence in massively scalable data centers.  We believe these environments will see further benefits with the performance visibility tools we’re building into our portfolio, as well as the programmability and automation features in the Cisco ONE offering.

We also believe that there is an important role for custom silicon in the software-defined networking world. We feel that customers will continue to be willing to pay for advanced hardware innovation because of the value they derive from tightly integrating advanced software and hardware engineering.  Customers derive the greatest value from emerging software approaches, such as SDN, when they effectively leverage the underlying infrastructure which Cisco silicon innovation enables them to do.

Additionally, the 190 nanosecond ultra low latency of the Nexus 3548 switch enables applications to innovate not only to High Performance Trading Fabrics but also into Massively Scalable Data Center,   Software Defined Network, and beyond.


I’d like to thank Chih-Tsung for this valuable information. To see an actual Algo Boost powered ASIC, view the TechWiseTV segment below..


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