In my prior blog entry, I mentioned two blog articles of interest that I had read recently, and then proceeded to comment on one of them. I’ll finally finish up and comment on the other one: Blowing the Doors of HPC Speed-up Numbers, written by Head Monkey Douglas Eadline (disclaimer: I used to write the MPI Mechanic column and Doug would edit it before it hit the shelves in the now-defunct Cluster World magazine).
I actively read a bunch of HPC-related news feeds and blogs out there in the interwebs (how did I live before my RSS reader?). Two articles recently caught my attention:
Don’t get me wrong; I read lots of fine articles and blog entries. But these two seemed to resonate fairly well with some of the messages I’ve tried to convey here in my own blog.
A colleague recently told me that he took two round trip flights from California to Florida for the sole purpose of nudging him into the next frequent flyer status level (over 100,000 miles in a year, in his case). “At the time, I questioned the wisdom waking up early enough to get on a plane at 6am on a Saturday morning,” he said. “But I’ve been automatically upgraded to first class ever since. So — good decision.” Even more surprising is that, by random chance, he found another guy who took both of the same flights for exactly the same reason.
Parallel programming is kinda like that. If you’re just venturing into a concurrent programming world, it seems weird, awkward, and possibly even counter-intuitive. But once you learn how to do it right, the benefits are continual. And you’ll find that others are doing the same thing.
Do you know what an iBarrier is?
- A joke in the MPI Forum
- A useful synchronization technique
- Waiting in line at the Apple store for an iPhone
For a long time, the answer was #1 — we jokingly referred to “non-blocking barriers” in the same breath as MPI_SEND_ANY and MPI_ESP(do_what_i_meant_not_what_i_coded). But recently, the answer has become #2.
Lots of interesting things were announced at the International Supercomputing Conference (ISC’10) this week. Sadly, I wasn’t there; I was just reading the press releases, tweets, blogs, and watching the vlogs like everyone else who wasn’t there.
I’ll pick just one topic to discuss here: the Intel Many Integrated Cores (MIC) announcement.