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How the World’s Most Advanced Network Processor is Making the Internet of Everything Possible

- September 12, 2013 - 28 Comments

Over the last 30 years the Internet has transformed multiple times. Most of us take it for granted these days. We expect to watch videos on Netflix, run our meetings over WebEx, talk to our friends across the globe on Skype, and have access whether we’re at work, home, or on the go. But we forget that the Internet wasn’t originally built for this – it’s been barely 20 years since email, the World Wide Web, and always-on network access have become realities. The changes have occurred at a dizzying pace.

In the beginning the only way to handle the work of the Internet – routing and forwarding packets – was by using general-purpose computer chips. This didn’t last long as the explosive growth in network bandwidth drove Cisco and other infrastructure providers to use more customized silicon. Indeed, Cisco’s market success was driven in large part by our ability to offer industry-leading solutions with the best combination of price, performance, and capabilities. This in turn was fueled by Cisco’s use of internally developed network silicon using advanced ASIC development models ahead of competitors who continued to rely on general purpose CPUs or FPGAs to power their products.

Now the Internet is on the cusp of another transformation and this one will make it central to society and how we live, work, and play. We call it the Internet of Everything (IoE). While an important consequence of IoE will be a dramatic increase in network bandwidth, the nature of the network will itself change. Interactions will be between people, processes, and things and at any time the network will be simultaneously processing trillions of “network events”.

Cisco Announced nPower X1 Chip

The Internet of Everything will require extremely advanced silicon and it begins today with the launch of the world’s most scalable and programmable network processor, the Cisco nPower™ X1. With over 4 billion transistors, this highly integrated 400 Gbps throughput single-chip will enable Terabit class solutions. It has sophisticated programmable control using open APIs and advanced compute operations that makes it ideal for software defined networks while handling extremely high event rates. It will help simplify network operations and allow new business models while it enables our customers to both support rapid bandwidth growth and transform the Internet.

The nPower journey has just begun. X1 is the first in a family and our team is well along in the development of even more advanced devices in this groundbreaking architecture.

Cisco will introduce networking innovations featuring the nPower X1 during a media, analyst and industry webcast on Tuesday, September 24, from 8:00 a.m. to 9:15 a.m. PDT.  To register, please visit


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  1. Will this product be used in Edge routers?

    • Stay tuned for more details on Sept 24:

    • Hi Andy, As its mentioned,a single chip will handle a throughout of 400Gbps, I don't think it will be deployed in edge/access routers.But we can't predict the growth of internet. As Nikhil mentioned we need to wait for 24th sep for the formal introduction by CISCO. Thanks

  2. What has this got to do with M2M?

    • Everything. You'll find out why on Sept. 24:

      • This has to be the most uninformative product launch ever..

        • As mentioned, we will provide more details on September 24th if you'd like to register for the live event:

  3. Will this also be used in security appliances like the ASAs?

    • Stay tuned on Sept 24 and you'll know what we've got planned:

  4. What does this mean for EZ-Chip?

  5. Very Interesting Nikhil, glad you guys finally got this beast up and running and out the door. Looking forward to seeing it follow the same success as we did with the QFP !

  6. From a pure processor capacity perspective, is this superior to the commercial silicon which seats into the Arista Networks switches?

    • For now we'd rather mention the capabilities of nPower X1 and leave the comparisons for another time. The nPower X1 is a high-scale, high-performance, fully programmable, highly integrated, L2-L7 single-chip network processor. Join the webcast on Sept 24 to learn more:

  7. Great, cannot wait to see the details on nPower X1 and IoE products. TV commercials have been super cool on IoE.

  8. Data plane or control plane?

    • Any network processor, almost by definition, has to support data plane functions. And if such a device is highly programmable then interesting applications that blur the lines between control and data planes can be supported.

  9. EZCH is down 30% since this announcement. It might be a nice courtesy for Cisco to say something if the relationship is going to change.

    • In the interest of focusing my discussion on the technology and the markets, I encourage you to reach out to the appropriate contact here:

  10. Wow, developmental or technological transformation stronger and faster, this makes the internet world solit development of the past 10 thun of the need for work, shopping, learning etc.. Dependence on the value of Internet technologies that users will always solid in the world, thank you

  11. I can't wait for 24th i am really interested to know more about this.

  12. Dear Nikhil : I think if memory vendors able to designing and produce TCAM(Ternary Content Addressable Memory) memory, RLDRAM 2&3 and QDR-SRAM 2+ in 3d (stacking), also hardware designers using HMC (Hybrid Memory Cube), ASICs or FPGAs with 3D(stacking)structure and optical interlaken and optical backplanes big changing in high-end routers and switches, MPLS networks will be faster, improving performance and speed and reducing convergence time.

  13. Dear Nikhil : do you mean : FPGA + ASIC(CISCO IP) = Cisco nPower™ X1 ? Why Cisco doesn’t use xilinx FPGA or Achronix or Tabula (3D) or Tri-gate FPGA ? I think in SDN Networks, using 3D FPGAs Better than ASIC, FPGA is very flexible. Even cisco could using optical ASIC (Reflexphotonics) or FPGA (Altera optical FPGA), with optical Interlaken and optical backplanes (pci-ex or optical rapid i/o). FPGAs add comms cores amid ASIC debate : (EETIMES) Xilinx showcases 400G apps for optical and wired OTN Markets at OFC 2013 : (EETIMES)

    • Mohammad, This is to address both your comments on this blog. nPower X1 is a custom development and not an FPGA, but we do use FPGAs widely across Cisco's product portfolio. The explanation on why nPower is not in an FPGA would be the same one used for any custom development. The considerable value and benefits of an FPGA comes at the expense of cost, power, performance, levels of integration, etc. In some cases the calculus leads to an FPGA being used because those benefits carry more weight. In this case they didn't. We try to objectively pick the right silicon solution for a product or application. As a consequence, across the breadth of Cisco's product portfolio, we develop FPGAs, ASICs, and custom silicon. My team is involved in all three. We also use merchant silicon and general purpose CPUs as appropriate. There are a large number of dimensions to the evaluation including a variety of technical and roadmap factors. I agree with your assessment on the value of future technologies including advanced packaging and interconnects. Cisco is always working on next generation products, but we typically announce them only when production readiness is achieved.

  14. good ! developmental or technological transformation stronger and faster.

  15. Thanks for this article Nikhil! I'm realy impressed about this processor! I think 400 Gbps throughput single chip is a lot and that will make the data tranfer much faster! Best regards!

  16. I can't wait for this.

  17. Hi Nikhil, for some reasons I could not attend the discussion. Is there a written QA session uploaded? if yes, It would be great to have it. thanks, Pavan H I

    • Hi Pavan, You can watch the webcast here: Here is another video you might find interesting: Thanks.